The invention relates to the connection and exchange of digital information between electronic cards.
The invention applies advantageously but not limitingly to the so-called xe2x80x9cbackplanexe2x80x9d connection facility providing for the use of connection cards referred to as xe2x80x9cbackplane cardsxe2x80x9d installed in racks and on which are connected electronic cards comprising various components as a function of their application, such as microprocessors, for example.
At present, backplane cards are exclusively passive in the sense that they comprise only the connection facility proper and impedance matching means.
Furthermore, when for a particular rig, a user has defined a certain electronic configuration providing for a certain number of electronic cards to be connected together, he chooses a backplane card having sufficient connection areas to be able to connect the number of electronic cards which he envisaged at the outset. Moreover, he must also dimension the supply means of these electronic cards as a function of their initially envisaged number.
If for any reason the user has to increase the number of cards in his configuration, it is not possible for him to extend his backplane without having to modify everything and has furthermore to redimension the supply means.
Moreover, when these backplane cards form the hardware support for a digital linking bus conveying digital information between the electronic cards, the number of signals to be processed requires that complex decoding circuits, which are sometimes specific and which are often expensive, be installed on the electronic cards connected on the backplane card.
Finally, the need for these backplane cards to meet the constraints of electromagnetic immunity requires expensive solutions.
The invention aims to afford a solution to these problems.
The invention therefore proposes a process for exchanging digital information between electronic cards, in which the electronic cards are removably connected on at least one base card (or backplane card) comprising its own individual supply means connected on a printed circuit possessing a set of tracks for the flow of electrical signals able to convey the said information, and certain at least of the electrical signals flowing, on this base card, between the connection areas of the electronic cards are amplified directly on the base card.
The base card is therefore an active card insofar as it possesses its own individual amplification means comprising amplification barriers proper based on flip-flops or buffer memories and logic functions building in amplification, for example programmable logic circuits (or Programmable Array Logic).
Furthermore, this backplane card builds in its own individual supply which is dimensioned in such a way as to be able to supply the maximum number of electronic cards which can be connected on this base card. Whereas in theory a minimum of two electronic cards is connected on a base card, it is in practice possible to connect more than two, for example four, on equidistant connection areas.
To obtain a modular backplane, at least one other base card of similar structure can be connected on the base card. Thus, the user can add the base cards alongside one another so as to produce the configuration which he desires. If his configuration must alter over time, he can always add or remove one or more base cards. Furthermore, since each base card builds in a supply sufficient to supply the electronic cards which it can receive, it is not necessary to redimension a new specific supply, since the new base card also builds in its own individual supply. This further contributes to the perfect modularity of the backplane according to the invention.
Moreover, a connection of the base cards one on another is advantageously envisaged so that all the connection areas of the electronic cards, situated on the set of base cards, are equidistant. Thus, the general appearance of an electronic configuration composed of several electronic cards connected on several base cards, remains homogeneous.
Independently or not of the characteristics just alluded to, relating in particular to supply and to amplification, the process according to the invention advantageously provides for the said set of tracks of each base card to form a hardware support for a digital bus on which are conveyed, synchronously, data logic signals, address logic signals, as well as monitoring logic signals, with the exclusion of any clock logic signal such as is conventionally present in the digital buses known from the prior art. The absence of any clock signal conveyed on the bus contributes to assisting the electromagnetic immunity of the card conveying the bus, since the presence of numerous rising edges existing in a clock signal, especially at high frequency, is thus avoided. It then becomes possible to use simple means to obtain this immunity. Moreover, by providing a synchronous bus it becomes possible to obtain predetermined cycle times, this offering the advantage of being able to determine the duration of the various processing operations in advance.
Generally, when an exchange of information is envisaged between a so-called xe2x80x9cmasterxe2x80x9d electronic card, comprising an input/output port linked to a processing unit such as a processor, and at least one so-called xe2x80x9cslavexe2x80x9d electronic card, addressable by the processing unit, an address cue comprising a first address indication (for example a certain number of high-order bits of the address) making it possible to locate the slave card on the bus as well as a second address indication (low-order bits) defining an addressing space within the slave card, is associated with every slave card. The process according to the invention advantageously comprises at least write access cycles and read access cycles, in the course of which the following are conveyed in the guise of monitoring logic signals; an access logic signal representative of an access or non-access in read or write mode to the bus, an enabling logic signal allowing in particular enabling of the second address indications, this enabling logic signal being active at the high logic level throughout the duration of write or read access, and a selection logic signal activated by the slave card having recognized its address cue.
The process can furthermore comprise a step of resetting the slave cards, this reset step being performed in the presence of a reset logic signal emitted by the master card.
In order to ensure interoperability of the electronic cards which can be connected on one or more base cards, there is advantageously provision for the process according to the invention to be able to comprise automatic recognition of the electronic cards connected on the digital bus. Thus, this automatic recognition exonerates the user from the conventional manual and mechanical operations consisting in positioning jumpers on the electronic cards connected on the bus so as to contrive their first address indication mechanically.
More precisely, according to one mode of implementation of the process, an identifier representative of a card type chosen from among predefined types is stored in certain at least of the slave cards and provision is made for a step of automatic identification by the master card, of the type of each slave card connected on a base card, as well as a step of automatic assignment by the master card to each identified slave card of its first address indication making it possible to locate it on the bus.
In practice, a slave card intended to be identified automatically is equipped with an internal logic unit able to deliver in series a predetermined number of bits forming the said identifier. After the reset step, this slave card advantageously then sequentially transmits toward the master card the bits of its identifier by using the selection logic signal, and the master card then transmits to the slave card a predetermined number of address bits constituting the said first address indication.
When several slave cards are connected in parallel on one or more base cards, the master card advantageously identifies and addresses the slave cards sequentially in a pre-established order.
According to a preferred mode of implementation of the process according to the invention, each slave card intended to be identified automatically is equipped with an initialization input able to receive an initialization input logic signal, and with an initialization output able to deliver an initialization output logic signal. The initialization input of the first slave card is linked to the master card, and the initialization output of each slave card is linked to the initialization input of the next slave card in the said pre-established order. A card receiving an inactive initialization input logic signal then ignores any cue flowing on the bus. At the termination of the reset step, the initialization output logic signals of all the slave cards are inactive while only the initialization input logic signal of the first slave card is active. At the termination of the identification step and of the address assignment step relating to a current slave card, the initialization output logic signal delivered by this card becomes active then allowing the identification and address assignment of the next slave card.
The process can also comprise a step of transferring information between the master card and a slave card according to a so-called xe2x80x9cdirect memory accessxe2x80x9d mode controlled by three logic signals managed by the master card.
For all the modes of implementation of the process which have just been mentioned, it is particularly advantageous to control the clock inputs of the address decoding logic circuits installed on the slave cards directly on the rising edges of the enabling logic signal. Thus, programmable logic circuits with registers can be used directly and it is thus possible to minimize the number of components required on the electronic cards connected on the base cards.
When furthermore provision is made for exchanging information between a master electronic card comprising an input/output port linked to a master processing unit such as a master processor and at least one slave electronic card addressable by the processing unit and linked to a slave processing unit such as a slave processor, the master card can be permitted to send simultaneous requests to several slave cards but to receive a cue originating from only one slave card at a time. The mutual exclusion of the slave cards as regards the sending of their cues to the master card is then advantageously managed within management logic means installed directly on the slave cards.
These management logic means may comprise a programmable logic circuit, the clock input of which is controlled on the falling edge of the enabling logic signal in the presence of predetermined conditions.
The subject of the invention is also a system for connection between electronic cards, comprising at least one base card (or backplane card) comprising a printed circuit possessing a set of tracks for transferring electrical signals, at least two base connectors connected on the said set of tracks and each able removably to receive one of the said electronic cards, signal amplification means connected on the printed circuit, and individual electrical supply means connected on the printed circuit and able to supply the amplification means and the said electronic cards.
According to an advantageous embodiment, the base card comprises more than two base connectors, and preferably four, all connected in parallel on the said set of tracks, the amplification means being arranged between two of the base connectors.
In order to assist with the modularity of the backplane, the base card advantageously furthermore comprises first and second complementary extension connectors connected on the said set of tracks and arranged on either side of the amplification means. The first extension connector of the base card is able to cooperate removably with a second extension connector on another base card while the second extension connector of the base card is able to cooperate removably with a first extension connector of another base card.
According to one embodiment of the invention, the two extension connectors are arranged transversely in the vicinity of two opposite ends of the base card.
The base card preferably comprises at the level of the tracks of the printed circuit groups of transverse rows of connection holes, each group being able to receive pins of a base connector or extension connector. The transverse rows of one and the same group being mutually spaced longitudinally by a distance equal to an integer multiple of a predetermined spacing pitch. Two adjacent rows belonging respectively to two neighboring groups assigned to two base connectors are spaced apart by an integer multiple of the said spacing pitch while two adjacent rows belonging to two neighboring groups respectively assigned to a base connector and to an extension connector are spaced apart by a distance equal to one and a half times the spacing pitch.
Such an arrangement of the connection holes on the base cards makes it possible, on the one hand, to obtain an equidistance between the base connectors of each base card and, on the other hand, an equidistance between all the base connectors of several base cards assembled together by way of their extension connectors.
The printed circuit is a double-faced circuit, the set of tracks, the connectors and the amplification means advantageously being situated exclusively on one of the faces while the other face comprises other so-called xe2x80x9cgroundxe2x80x9d tracks forming a ground plane, this promoting the electromagnetic immunization of the cards.
According to one embodiment of the invention, the amplification means comprise a first bidirectional amplification circuit able to amplify the data signals and a part of the address signals of the bus, and possessing a control input terminal for defining the direction of travel of the signals through this first circuit. The amplification means also comprise a bidirectional programmable logic circuit able to amplify a part of the control signals and an output terminal of which is linked to the control input terminal of the first amplification circuit. The amplification means finally comprise a second amplification circuit functioning in monodirectional mode able to amplify another part of the address signals and the remaining control signals. These three circuits are arranged on the same face of the printed circuit and the programmable logic circuit is arranged between the first bidirectional amplification circuit and the second monodirectional amplification circuit.
This mechanical and logic layout of the amplification means makes it possible both to obtain a double-faced printed circuit on the base cards and on the electronic cards intended to be connected therewith, it being possible for the other face of the printed circuit of these cards to be assigned to a ground plane.